This invention generally relates to electronic circuits, and more specifically to nonvolatile semiconductor integrated circuits.
Nonvolatile memory circuits such as electrically erasable programmable read only memories (EEPROM) and Flash EEPROMs have been widely used for several decades in various circuit applications including computer memory, automotive applications, and video games. Many new applications, however, require the access time and packing density of previous generation nonvolatile memories in addition to low power consumption for battery powered circuits. One nonvolatile memory technology that is particularly attractive for these low power applications is the ferroelectric memory cell. A major advantage of these ferroelectric memory cells is that they require approximately three orders of magnitude less energy for write operations than previous generation floating gate memories. Furthermore, they do not require high voltage power supplies for programming and erasing charge stored on a floating gate. Thus, circuit complexity is reduced and reliability increased.
The term ferroelectric is something of a misnomer, since present ferroelectric capacitors contain no ferrous material. Typical ferroelectric capacitors include a dielectric of ferroelectric material formed between two closely-spaced conducting plates. One well-established family of ferroelectric materials known as perovskites has a general formula ABO3. This family includes Lead Zirconate Titanate (PZT) having a formula Pb(ZrxTi1xe2x88x92x)O3. This material is a dielectric with a desirable characteristic that a suitable electric field will displace a central atom of the lattice. This displaced central atom, either Titanium or Zirconium, remains displaced after the electric field is removed, thereby storing a net charge. Another family of ferroelectric materials is Strontium Bismuth Titanate (SBT) having a formula SbBi2Ta2O9. SBT has several advantages over PZT. However, both ferroelectric materials suffer from fatigue and imprint. Fatigue is characterized by a gradual decrease in net stored charge with repeated cycling of a ferroelectric capacitor. Imprint is a tendency to prefer one state over another if the ferroelectric capacitor remains in that state for a long time as will be discussed in detail.
A typical one-transistor, one-capacitor (1T1C) ferroelectric memory cell of the prior art is illustrated at FIG. 1. The ferroelectric memory cell is similar to a 1T1C dynamic random access memory (DRAM) cell except for ferroelectric capacitor 100. The ferroelectric capacitor 100 is connected between plateline 110 and storage node 112. Access transistor 102 has a current path connected between bitline 108 and storage node 112. A control gate of access transistor 102 is connected to wordline 106 to control reading and writing of data to the ferroelectric memory cell. This data is stored as a polarized charge corresponding to cell voltage VCAP. Capacitance of bitline BL is represented by capacitor CBL 104.
Referring to FIG. 2, there is a hysteresis curve corresponding to the ferroelectric capacitor 100. The hysteresis curve includes net charge Q or polarization along the vertical axis and applied voltage along the horizontal axis. By convention, the polarity of the ferroelectric capacitor voltage is defined as shown in FIG. 1. A stored xe2x80x9c0xe2x80x9d, therefore, is characterized by a positive voltage at the plateline terminal with respect to the access transistor terminal. A stored xe2x80x9c1xe2x80x9d is characterized by a negative voltage at the plateline terminal with respect to the access transistor terminal. A xe2x80x9c0xe2x80x9d is stored in a write operation by applying a voltage Vmax across the ferroelectric capacitor. This stores a saturation charge Qs in the ferroelectric capacitor. The ferroelectric capacitor, however, includes a linear component in parallel with a switching component. When the electric field is removed, therefore, the linear component discharges and only the residual charge Qr remains in the switching component. The stored xe2x80x9c0xe2x80x9d is rewritten as a xe2x80x9c1xe2x80x9d by applyingxe2x88x92Vmax to the ferroelectric capacitor. This charges the linear and switching components of the ferroelectric capacitor to a saturation charge of xe2x88x92Qs. The stored charge reverts to xe2x88x92Qr when the voltage across the ferroelectric capacitor is removed. Finally, coercive points VC and xe2x88x92VC are minimum voltages on the hysteresis curve that will degrade a stored data state. For example, application of VC across a ferroelectric capacitor will degrade a stored xe2x80x9c1xe2x80x9d even though it is not sufficient to store a xe2x80x9c0xe2x80x9d. Thus, it is particularly important to avoid voltages near these coercive points unless the ferroelectric capacitor is being accessed.
Referring to FIG. 3, there is illustrated a typical write sequence for a ferroelectric memory cell as in FIG. 1. Initially, the bitline (BL), wordline (WL), and plateline (PL) are all low. The upper row of hysteresis curves illustrates a write xe2x80x9c1xe2x80x9d and the lower row represents a write xe2x80x9c0xe2x80x9d. Either a xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d is initially stored in each exemplary memory cell. The write xe2x80x9c1xe2x80x9d is performed when the bitline BL and wordline WL are high and the plateline PL is low. This places a negative voltage across the ferroelectric capacitor and charges it to xe2x88x92Qs. When plateline PL goes high, the voltage across the ferroelectric capacitor is 0 V, and the stored charge reverts to xe2x88x92Qr. At the end of the write cycle, both bitline BL and plateline PL go low and stored charge xe2x88x92Qr remains on the ferroelectric capacitor. Alternatively, the write xe2x80x9c0xe2x80x9d occurs when bitline BL remains low and plateline PL goes high. This places a positive voltage across the ferroelectric capacitor and charges it to Qs representing a stored xe2x80x9c0xe2x80x9d. When plateline PL goes low, the voltage across the ferroelectric capacitor is 0 V, and the stored charge reverts to Qr representing a stored xe2x80x9c0xe2x80x9d.
A read operation is illustrated at FIG. 4 for the ferroelectric memory cell at FIG. 1. The upper row of hysteresis curves illustrates a read xe2x80x9c0xe2x80x9d. The lower row of hysteresis curves illustrates a read xe2x80x9c1xe2x80x9d. Wordline WL and plateline PL are initially low. Bitlines BL are precharged low. At time xcex94t0 bitline precharge signal PRE goes low, permitting the bitlines BL to float. At time xcex94t1 both wordline WL and plateline PL go high, thereby permitting each memory cell to share charge with a respective bitline. A stored xe2x80x9c1xe2x80x9d will share more charge with parasitic bitline capacitance CBL and produce a greater bitline voltage than the stored xe2x80x9c0xe2x80x9d as shown. A reference voltage (not shown) is produced at each complementary bitline of an accessed bitline. This reference voltage is between the xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d voltages. Sense amplifiers are activated at the time boundary between xcex94t1 and xcex94t2. When respective bitline voltages are fully amplified in time xcex94t2, the read xe2x80x9c0xe2x80x9d curve cell charge has increased from Qr to Qs. By way of comparison, the read xe2x80x9c1xe2x80x9d data state has changed from a stored xe2x80x9c1xe2x80x9d to a stored xe2x80x9c0xe2x80x9d. Thus, the read xe2x80x9c0xe2x80x9d operation is nondestructive, but the read xe2x80x9c1xe2x80x9d operation is destructive. At time xcex94t3, plateline PL goes low and applies xe2x88x92Vmax to the read xe2x80x9c1xe2x80x9d cell, thereby storing xe2x88x92Qs. At the same time, zero voltage is applied to the read xe2x80x9c0xe2x80x9d cell and charge Qr is restored. At the end of time xcex94t3, signal PRE goes high and precharges both bitlines BL to zero volts or ground. Thus, zero volts is applied to the read xe2x80x9c1xe2x80x9d cell and xe2x88x92Qr is restored.
Referring to FIGS. 5A and 5B, there are timing diagrams illustrating two different types of sensing that may be used in ferroelectric memory circuits. A primary difference between these two schemes is that the step sensing scheme (FIG. 5A) uses a single pulse of plateline PL, while the pulse sensing scheme (FIG. 5B) uses a double pulse of plateline PL. For both types of sensing, bitline precharge signal PRE goes low at time t0, thereby permitting the bitlines BL to float. Next, wordline WL goes high at time t1 to turn on access transistors of a row of memory cells. Plateline PL goes high between times t1 and t2, permitting ferroelectric memory cells share charge with their respective bitlines BL and develop respective difference voltages. Here, V1 represents a data xe2x80x9c1xe2x80x9d and V0 represents a data xe2x80x9c0xe2x80x9d. The difference voltage available for sensing is the difference between one of V1 and V0 and a reference voltage (not shown) which lies approximately midway between voltages V1 and V0. This difference voltage is amplified at time t3 for the step sensing scheme (FIG. 5A) so that full bitline BL voltages are developed before the plateline PL goes low at time t4. The data xe2x80x9c0xe2x80x9d cell is fully restored between time t3 and time t4 while plateline PL is high and the data xe2x80x9c0xe2x80x9d bitline BL is low. At time t4, the plateline PL goes low while the data xe2x80x9c1xe2x80x9d bitline BL remains high. Thus, the data xe2x80x9c1xe2x80x9d cell is restored between time t4 and time t5. Bitline precharge signal PRE goes high at time t5, thereby precharging the bitlines BL to ground or 0 V. The step sensing cycle is completed when wordline WL goes low at time t6 to store respective data in the row of memory cells.
Referring now to FIG. 5B, the first pulse of plateline PL develops a difference voltage at time t2. Plateline PL then goes low at time t3, and the common mode difference voltage goes to near 0 V. Then the difference voltage is amplified at time t4, and full bitline BL voltages are developed while the plateline PL is low. Thus, the data xe2x80x9c1xe2x80x9d cell is restored between time t4 and time t5 while plateline PL is low and the data xe2x80x9c1xe2x80x9d bitline BL is high. At time t5, the plateline PL goes high while the data xe2x80x9c0xe2x80x9d bitline BL remains low. Thus, the data xe2x80x9c0xe2x80x9d cell is restored between time t5 and time t6. The data xe2x80x9c1xe2x80x9d cell is again restored between time t6 and time t7 while plateline PL is low and the data xe2x80x9c1xe2x80x9d bitline BL is high. Bitline precharge signal PRE goes high at time t7, thereby precharging the bitlines BL to ground or 0 V. The pulse sensing cycle is completed when wordline WL goes low at time t8.
Turning now to FIG. 6, there is a plateline PL drive circuit of the prior art. The drive circuit comprises a CMOS inverter formed by P-channel transistor 600 and N-channel transistor 602. The input terminal 604 of the inverter is coupled to receive plate line control signal /CTL_PLT. The inverter output terminal 606 is connected to parasitic plate capacitor CPLATE 608, and produces plateline signal PL (FIG. 5). Parasitic plate capacitor CPLATE 608 preferably represents capacitance of a plateline for at least a portion of a wordline of ferroelectric memory cells. As such, this large plateline capacitance CPLATE 608 requires large drive transistors 600 and 602 to minimize plateline PL rise and fall times, thereby minimizing sense and write cycle times. Since N-channel transistors typically have at least twice the mobility of P-channel transistors, the N-channel transistor typically has a width W/2 that is one-half the width W of the P-channel transistor, thereby providing approximately the same rise and fall times of plateline signal PL. A problem with this plate drive circuit of the prior art occurs, however, when the plateline PL of a ferroelectric memory cell goes from high to low on a bitline BL that is also driven low. For example, the pulse sensing scheme of FIG. 7 illustrates the double pulse of the plateline PL. During the first high-to-low transition of plateline PL at time t1, the bitline BL is floating as described at FIG. 5B. During the second high-to-low transition of plateline PL at time t3, however, the bitline BL is driven low to restore a data xe2x80x9c0xe2x80x9d, and induces significant gate oxide stress, as will be explained in detail, on N-channel pass gate transistor 102 (FIG. 1). This gate oxide stress poses a significant long-term reliability hazard, since the high-to-low transition of plateline PL for a driven low bitline BL will happen for approximately half of all read and write operations.
Referring now to FIG. 8, there is a simplified diagram to illustrate the induced gate oxide stress on N-channel pass gate transistor 102. Here, the same reference numerals are used as in FIG. 1 to show comparable elements of the ferroelectric memory cell. During any read or write operation of a data xe2x80x9c0xe2x80x9d, bitline BL 108 is driven low and plateline PL 110 is driven high to restore or write a data xe2x80x9c0xe2x80x9d on ferroelectric capacitor 100. During burn-in, preferable wordline voltages at the gate terminal 106 and plateline voltage at terminal 110 are both 2.5 V. Resistance RGATE 114 of N-channel pass gate transistor 102 is approximately 500xcexa9. Ferroelectric capacitor 100 has a value of approximately 30 fF. A rapid transition of plateline terminal 110 from 2.5 V to 0 V over a 100 ps period will induce an average current through resistor RGATE 114 of about 1400 xcexcA. This current will develop xe2x88x920.7 V at storage node 112, the source of N-channel pass gate transistor 102. The resulting gate-to-source voltage of N-channel pass gate transistor 102 is 3.2 V. This produces an excessive electric field across the gate oxide between the gate 106 and source 112 terminals, and poses a significant reliability hazard. Moreover, at a source voltage of xe2x88x920.7 V, the parasitic source-to-substrate diode 116 is strongly forward biased and will inject a substantial number of minority carriers (electrons) into the substrate. The resulting injection from a row of memory cells may be sufficient to induce latchup between parasitic PNP and NPN transistors in the CMOS circuit. Moreover, the injection may reduce local substrate bias, thereby reducing access transistor threshold voltages of nearby unaccessed memory cells. Even during normal circuit operation, the average current through resistor RGATE 114 is about 300 xcexcA. The corresponding wordline voltage at terminal 106 is 2.0 V, and xe2x88x920.15 V is induced on storage node 112. Thus, even under normal operating conditions, the high-to-low transition of plateline terminal 110 develops 2.15 V across the gate oxide of N-channel pass gate transistor 102. This is well above the normal maximum wordline voltage and also poses a long-term reliability hazard for the ferroelectric memory cell.
In accordance with a preferred embodiment of the invention, there is disclosed a memory circuit for reducing gate oxide stress. The circuit comprises a memory cell for storing data. The memory cell has a first and a second control terminal and a pass gate transistor. The pass transistor has a control gate coupled to the first control terminal. The memory circuit includes a drive circuit having an output terminal coupled to the second control terminal. The drive circuit is arranged to produce a control signal having a rise time and a fall time, wherein the fall time is greater than the rise time. The increased fall time reduces negative voltage at the source of the pass transistor, thereby reducing gate-to-source voltage and gate oxide stress.